The present invention relates generally to flash memory arrays and more specifically to a method and system for fabricating a flash memory array.
Semiconductor manufacturers have increasingly turned to high density flash memory arrays in their integrated circuit design schemes. To achieve a high density integrated circuit, the transistors must be as small as possible. Typically, these high density flash memory integrated circuits utilize NAND-type gates as opposed to NOR-type gates since NAND gates have a considerably higher density than NOR gates. Smaller transistors allow more transistors to be placed on a single substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
When fabricating silicon integrated circuits, devices built onto the silicon must be isolated from one another so that these devices can be subsequently interconnected to create specific circuit configurations. From this perspective, it can be seen that isolation technology is one of the critical aspects of fabricating integrated circuits.
During the manufacturing of integrated circuit devices, the devices are isolated from one another through a combination of a thick field oxide (FOX) and channel doping. For advanced deep submicronmeter and high density flash memory technology, a duel field oxidation process, or LOCOS (LOCal Oxidation of Silicon), is usually required to optimize transistor isolation.
FIG. 1 is a flow chart illustrating the conventional process steps required to fabricate a NAND flash memory array. Also shown is a series of cross sectional views (FIGS. 1(a-g)) of a substrate showing the resulting structure.
The LOCOS process begins by thermally growing a layer of oxide on the surface of bare silicon, via step 10. Next, a nitride layer is provided over the layer of oxide, via step 12. This layer of nitride has a typical thickness in the range of around 1700 Angstroms. Then, the nitride layer is etched down to the oxide layer to define the active regions, via step 14. Next, using the nitride layer as a mask, a thin field oxide region (FOX) is grown between active regions using a thermal oxidation process, via step 16. Typically, the resulting step height 22 (see FIG. 1(d)) of the oxide region is between 1500 and 2500 Angstroms. Next, the nitride layer is stripped, via step 18. A layer of type-1 polysilicon (polyl) is then deposited, via step 20. Next, the polyl is etched down to the oxide region to define the channel area, via step 22.
When utilizing this process, channel misalignments have a tendency to occur. This is due primarily to the smaller spacings of the high density flash memory arrays. A channel misalignment occurs when the channel area is not defined directly in the middle of the FOX region. FIG. 2(a) illustrates a properly aligned channel area 24 and FIG. 2(b) illustrates a misaligned channel area 24xe2x80x2.
The etching process in step 22 is anisotropic, meaning that it removes material directionally to a predetermined depth. But due to the size of the step height of the FOX regions, along with the occurrences of channel misalignments, the etching process sometimes fails to remove all the polyl from the channel region, leaving a residue material which is called a poly 1 stringer. FIGS. 3(a-c) show the formation of polyl stringers after the polyl etch. The presence of polyl stringers can provide a contact between the two adjacent regions and failure to remove this material can lead to unwanted electrical shorting paths between the adjacent regions.
Utilizing the NOR technology, the polyl stringers are not a problem because steps that are implemented later in the NOR process (i.e. dipping steps, oxidation steps), effectively eliminate the polyl stringers. However, as previously mentioned, the NAND process is utilized for high density flash memory integrated circuits since NAND gates have a considerably higher density than NOR gates. Consequently, the NAND process does not incorporate later steps to effectively eliminate the polyl stringers.
Accordingly, what is needed is a method for reducing the occurrence of polyl stringers in the fabrication of flash memory arrays. The present invention addresses such a need.
In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced.
In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back.
Through the use of the preferred embodiment of the present invention, a shallow trench isolation process is implemented as opposed to LOCOS process, thereby reducing the occurrence of polyl stringers in the channel area. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent regions is substantially reduced.